1. Field of the Invention
The present invention relates to a W (double) cell type EEPROM (electrically erasable programmable read only memory).
2. Description of the Related Art
An EEPROM is known as a representative example of a nonvolatile memory. There are EEPROMs that employ a W cell system in which the same data are held in two memory cells (memory transistors). With a W cell type EEPROM, even when one of the memory cells malfunctions, data can be read from and written into the other memory cell.
FIG. 21 is a schematic plan view of a conventional W cell type EEPROM. FIG. 22 is a schematic sectional view taken on cutting line XXII-XXII of the EEPROM shown in FIG. 21. FIGS. 23 and 24 are circuit diagrams of the EEPROM shown in FIG. 21.
The EEPROM includes a P type silicon substrate 101. A first insulating film 102, made of SiO2 (silicon oxide), is formed on the silicon substrate 101. Further, in a top layer portion of the silicon substrate 101, an element isolation portion 103 is formed at a portion excluding an active region 104 with a rectangular shape in plan view. In FIG. 21, an outline of the active region 104 is indicated by thick lines. The element isolation portion 103 has, for example, a structure in which an insulator is embedded in a shallow trench formed by digging comparatively shallowly from the top surface.
In top layer portions of the silicon substrate 101 in the active region 104, five N type impurity regions 105 to 109 are formed and aligned at predetermined intervals in a longitudinal direction of the active region 104. The impurity regions 105 to 109 that are aligned from one end side to another end side in the longitudinal direction of the active region 104 shall be the first to fifth impurity regions 105 to 109, respectively.
On the first insulating film 102, a first select gate 110 is formed in a line-like manner extending in a direction orthogonal to the longitudinal direction of the active region 104 at a position opposing a region between the first impurity region 105 and the second impurity region 106. Further, on the first insulating film 102, a first floating gate 111 is formed at a position opposing a region between the second impurity region 106 and the third impurity region 107. A second insulating film 112, made of SiO2, is formed on the first floating gate 111. On the second insulating film 112, a first control gate 113 is formed in a line-like manner extending in a direction orthogonal to the longitudinal direction of the active region 104. In the first insulating film 102, a first tunnel window 114 is formed by decreasing a thickness of a part of a portion sandwiched between the second impurity region 106 and the first floating gate 111.
The EEPROM is thus provided with a first select transistor STr1, which includes the first impurity region 105, the second impurity region 106 and the first select gate 110, and a first memory transistor MTr1, which includes the second impurity region 106, the third impurity region 107, the first floating gate 111 and the first control gate 113, as shown in FIGS. 23 and 24.
Further, as shown in FIGS. 21 and 22, on the first insulating film 102, a second select gate 115 is formed in a line-like manner extending in a direction orthogonal to the longitudinal direction of the active region 104 at a position opposing a region between the third impurity region 107 and the fourth impurity region 108. Still further, on the first insulating film 102, a second floating gate 116 is formed at a position opposing a region between the fourth impurity region 108 and the fifth impurity region 109. A third insulating film 117, made of SiO2, is formed on the second floating gate 116. On the third insulating film 117, a second control gate 118 is formed in a line-like manner extending in a direction orthogonal to the longitudinal direction of the active region 104. In the first insulating film 102, a second tunnel window 119 is formed by decreasing a thickness of a part of a portion sandwiched between the fourth impurity region 108 and the second floating gate 116.
The EEPROM is thus provided with a second select transistor STr2, which includes the third impurity region 107, the fourth impurity region 108 and the second select gate 115, and a second memory transistor MTr2, which includes the fourth impurity region 108, the fifth impurity region 109, the second floating gate 116 and the second control gate 118, as shown in FIGS. 23 and 24. The first memory transistor MTr1 and the second select transistor STr2 are connected by the third impurity region 107, which is a source region of the first memory transistor MTr1, being used in common as a drain region of the second select transistor STr2.
As shown in FIG. 22, an interlayer insulating film 120 is laminated on the silicon substrate 101. The first insulating film 102, the first select gate 110, the first control gate 113, the second select gate 115 and the second control gate 118 are covered all together by the interlayer insulating film 120. In the interlayer insulating film 120, contact plugs 121 to 123 for respectively connecting the first impurity region 105, the third impurity region 107 and the fifth impurity region 109 with wirings (not shown) formed on the interlayer insulating film 120, are embedded.
As shown in FIG. 23, when data are to be written into the first memory transistor MTr1, the first control gate 113, the second select gate 115 and the second control gate 118 are set to a ground potential (GND). Further, the third impurity region 107, which is the source region of the first memory transistor MTr1, and the fifth impurity region 109, which is the source region of the second memory transistor MTr2, are set to an open state (OPEN). Then, a programming voltage Vpp (for example, 15 to 20V) is applied to the first impurity region 105, which is the drain region of the first select transistor STr1, and to the first select gate 110. The first select transistor STr1 is thereby turned on and a high electric field is formed between the second impurity region 106, which is the drain region of the first memory transistor MTr1, and the first floating gate 111. When this high electric field is formed, electrons are drawn from the first floating gate 111 into the second impurity region 106, and writing of data into the first memory transistor MTr1 is thereby achieved.
Meanwhile, as shown in FIG. 24, when data are to be written into the second memory transistor MTr2, the second control gate 118 is set to the ground potential (GND). Further, the fifth impurity region 109, which is the source region of the second memory transistor MTr2, is set to the open state (OPEN). Then, the programming voltage Vpp is applied to the third impurity region 107, which is the drain region of the second select transistor STr2, and to the second select gate 115. The second select transistor STr2 is thereby turned on and a high electric field is formed between the fourth impurity region 108, which is the drain region of the second memory transistor MTr2, and the second floating gate 116. When this high electric field is formed, electrons are drawn from the second floating gate 116 into the fourth impurity region 108, and writing of data into the second memory transistor MTr2 is thereby achieved.
In this state, the first impurity region 105, which is the drain region of the first select transistor STr1, is set to the open state, and the first select gate 110 and the first control gate 113 are set to the ground potential. However, the first memory transistor MTr1 is turned on because the program voltage Vpp, which is a comparatively high voltage, is applied to the third impurity region 107 which is the source region of the first memory transistor MTr1. A high electric field is thereby formed across the second impurity region 106, which is the drain region of the first memory transistor MTr1, and the first floating gate 111, and electrons may be drawn from the first floating gate 111 into the second impurity region 106.
Further, depending on a state (electron accumulation state) of the first floating gate 111, a current leaks from the third impurity region 107, which is the source region of the first memory transistor MTr1, to the second impurity region 106, which is the drain region, thereby causing reduction of efficiency of writing data into the second memory transistor MTr2 (loss of the programming voltage Vpp applied to the third impurity region 107).
Still further, with the conventional EEPROM, data cannot be written simultaneously into the two transistors of the first memory transistor MTr1 and the second memory transistor MTr2, and there is thus a problem that the writing of data takes time.